1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device incorporating a monolithic temperature sensor therein.
2. Description of the Related Art
In recent years, demands for monitoring an operating temperature of a semiconductor integrated circuit device have increased. This monitoring aims to prevent breakdown of a device in the semiconductor integrated circuit device by heat and/or to stabilize the operation of a device having characteristics changing in accordance with a temperature of a quartz oscillator or the like in a case where such a device is provided in the semiconductor integrated circuit device.
For example, Japanese Patent Laid-Open Publication No. Hei 1-302849 discloses a technique in which a temperature sensor is provided on the same substrate as an LSI (Large Scale Integrated circuit) in the semiconductor integrated circuit device. According to this technique, when the temperature detected by that temperature sensor exceeds a predetermined temperature, it is determined that abnormal overheating occurs and therefore the LSI is shut off so as to prevent thermal breakdown of the LSI caused by the temperature increase.
Moreover, Japanese Patent Laid-Open Publication No. Hei 9-229778 discloses a technique in which a parasitic PN-junction diode is used as the above temperature sensor, for example. FIG. 1 is a cross-sectional view of a conventional semiconductor integrated circuit device including a temperature sensor described in Japanese Patent Laid-Open Publication No. Hei 9-229778, and FIG. 2 is an equivalent circuit diagram of a temperature sensor portion of the conventional semiconductor integrated circuit device shown in FIG. 1.
As shown in FIG. 1, this conventional semiconductor integrated circuit device 21 is formed by a P-type silicon substrate P-Sub and a multilayer interconnection layer M21 formed on the P-type silicon substrate P-Sub. The multilayer interconnection layer M21 is formed by alternately depositing a plurality of wiring layers and a plurality of insulation layers. In this semiconductor integrated circuit device 21, an integrated circuit portion 2 is provided in a predetermined region of a surface of the P-type silicon substrate P-Sub and a predetermined region of the multilayer interconnection layer M21, and a temperature sensor portion 23 is provided in a region of the surface of the P-type silicon substrate PSub and a region of the multilayer interconnection layer M21, in which the integrated circuit portion 2 is not formed.
In the integrated circuit portion 2, a CMOS (Complementary Metal Oxide Semiconductor) circuit 4 is provided, for example. In the CMOS circuit 4, an N-well NW1 and a P-well PW1 are formed to be adjacent to each other on the surface of the P-type silicon substrate PSub. On the surface of the N-well NW1, two p+ diffused regions P1 and P2 serving as source/drain regions are formed to be spaced away from each other. On the surface of the P-well PW1, two n+ diffused regions N1 and N2 serving as source/drain regions are formed to be spaced away from each other. A region between the p+ diffused regions P1 and P2 in the N-well NW1 serves as a channel region 5. Similarly, a region between the n+ diffused regions N1 and N2 in the P-well PW1 serves as a channel region 6.
In regions of the multilayer interconnection layer 21 directly above the channel regions 5 and 6, a gate insulator (not shown) is provided. In regions on the gate insulator that are directly above the channel regions 5 and 6, gate electrodes G1 and G2 formed of polysilicon, for example, are provided, respectively. The gate electrodes G1 and G2 are connected to a gate terminal Vg that is common to the gate electrodes G1 and G2. In the above structure, the channel region 5, the p+ diffused regions P1 and P2 serving as the source/drain regions, the gate insulator, and the gate electrode G1 form a P-type MOS transistor. Similarly, the channel region 6, the n+ diffused regions N1 and N2 serving as the source/drain region, the gate insulator, and the gate electrode G2 form an N-type MOS transistor.
In a region of the multilayer interconnection layer M21 on the p+ diffused region P1, a via hole V1 is provided to connect with the p+ diffused region P1. On the via hole V1, a wiring W1 is provided to connect with the via hole V1. On the wiring W1, a via hole V2 is provided to connect with the wiring W1. On the via hole V2, a power-supply potential wiring Vcc is provided to connect with the via hole V2. Thus, the p+ diffused region P1 is connected to the power-supply potential wiring Vcc via the via hole V1, the wiring W1, and the via hole V2.
Moreover, in the multilayer interconnection layer M21, a via hole V3 is provided on the p+ diffused region P2 so as to connect with the P+ diffused region P2, and a via hole V4 is provided on the n+ diffused region N1 so as to connect with the n+ diffused region N1. On those via holes V3 and V4, a wiring W2 is provided to connect with both the via holes V3 and V4. On the wiring W2, a via hole V5 is provided to connect with the wiring W2. On the via hole V5, a wiring W3 is provided to connect with the via hole V5. In this manner, the p+ diffused region P2 and the n+ diffused region N1 are connected to the wiring W3 via the via holes V3 and V4, the wiring W2, and the via hole V5.
Furthermore, a via hole V6 is provided in a region of the multilayer interconnection layer M21 on the n+ diffused region N2 so as to connect with the n+ diffused region N1, and a wiring W4 is provided on the via hole V6 so as to connect with the via hole V6. On the wiring W4, a via hole v7 is provided to connect with the wiring W4. On the via hole V7, a ground potential wiring GND is provided to connect with the via hole V7. In this manner, the n+ diffused region N2 is connected to the ground potential wiring GND via the via hole V6, the wiring W4, and the via hole V7.
On the other hand, another p+ diffused region P3 is formed in a region on the surface of the P-type silicon substrate PSub other than the regions where the N-well NW1 and the P-well PW1 are formed. In a region of the multilayer interconnection layer M21 above the P+ diffused region P3, a via hole V8, a wiring W5, a via hole V9, and a ground potential wiring GND are provided in that order from the bottom, thereby the P+ diffused region P3 is connected to the ground potential wiring GND via the via hole V8, the wiring W5, and the via hole V9.
In the temperature sensor portion 23, an N-well NW2 is formed on the surface of the P-type silicon substrate PSub, and a p+ diffused region P21 and an n+ diffused region N21 are formed on the surface of the N-well NW2 to be spaced away from each other. In a region of the multilayer interconnection layer 21 above the P+ diffused region P21, a via hole 21, a wiring 21, a via hole 22 and a ground potential wiring GND are provided in that order from the bottom, thereby the P+ diffused region P21 is connected to the ground potential wiring GND via the via hole V21, the wiring W21, and the via hole V22.
In a region of the multilayer interconnection layer M21 above the n+ diffused region N21, a via hole V23 is provided to connect with the n+ diffused region N21, and a wiring W22 is provided on the via hole V23. The wiring W22 is connected to the via hole V23 at one end thereof and also connected to an output terminal Vout21. Under the wiring W22, a via hole V24 is provided to connect with the other end of the wiring W22. Under the via hole V24, a resistor R, formed of polysilicon, for example, is provided. The resistor R has a sheet-like shape and is connected to the via hole V24 at one end. The resistor R is formed simultaneously with the formation of the gate electrodes G1 and G2 of the CMOS circuit 4, and is therefore provided on the same level as the gate electrodes G1 and G2. Moreover, a via hole V25 is provided on the resistor R so as to connect with the other end of the resistor R. Furthermore, a wiring W23, a via hole V26, and a power-supply potential wiring Vcc are provided on the via hole V25 in that order from the bottom, thereby the resistor R is connected to the power-supply potential wiring Vcc via the via hole V25, the wiring w23, and the via hole V26.
Thus, a potential higher than that applied to the P+ diffused region P21 is applied to the N-well NW2. As a result, a forward PN junction is formed between the P+ diffused region P21 and the N-well NW2, thereby a parasitic PN-junction diode D is formed.
In the multilayer connection layer M21, the via holes V1, V3, V4, V6, V8, V21, and V23 are provided in the first insulation layer in which the gate electrodes G1 and G2 and the resistor R are also provided at the same level. Moreover, the wirings W1, W2, W4, W5, W21, W22, and W23 are provided in the first wiring layer provided on the first insulation layer to be at the same level mutually, and the via holes V2, V5, V7, V9, V22, and V26 are provided in the second insulation layer provided on the first wiring layer. In addition, the respective ground potential wirings GND, the respective power-supply potential wirings vcc, and the wiring W3 are provided in the second wiring layer provided on the second insulation layer to be at the same level mutually. Furthermore, regions of the multilayer interconnection layer M21, other than the respective via holes, the respective wirings, and the resistor R, and a layer positioned on the second insulation layer are filled with insulating material 7.
As shown in FIG. 2, in the temperature sensor portion 23 of the semiconductor integrated circuit device 21, the resistor R, and the parasitic PN-junction diode D are connected in series in that order from the power-supply potential wiring Vcc to the ground potential wiring GND, and the output terminal Vout21 is connected to a connection point between the resistor R and the parasitic PN-junction diode D. It should be noted that the parasitic PN-junction diode D is connected in the forward direction.
Thus, as shown in FIG. 1, when the temperature of the semiconductor integrated circuit device 21 changes, the characteristics of the parasitic PN-junction diode D also change. This change of the characteristics causes change of the potential at the output terminal Vout21. By detecting the potential at the output terminal Vout21, the temperature of the semiconductor integrated circuit device 21 can be measured. Moreover, in the semiconductor integrated circuit device 21, the parasitic PN-junction diode D can be formed by using a device structure of the MOS transistor. Therefore, the temperature sensor portion 23 can be formed without changing the conventional MOS process.
The conventional technique shown in FIGS. 1 and 2, however, has a problem that the temperature coefficient of the parasitic PN-junction diode D is as small as about 0.002/K and therefore a sufficient SNR (Signal-to-Noise Ratio) cannot be obtained.
Thus, a technique has been proposed in Japanese Patent Laid-Open Publication No. Sho 63-300523, for example, in which a temperature sensor having a structure other than the device structure of the MOS transistor, for example, a temperature sensor using a semiconductor capacitance, is provided in a semiconductor integrated circuit device.
However, this technique has the following problems. In order to monolithically form the temperature sensor having the structure other than the device structure of the MOS transistor in the semiconductor integrated circuit device, the conventional semiconductor process for forming the integrated circuit portion other than the temperature sensor portion has to be changed. This requires a development of new semiconductor process. Moreover, a macro for which the operation has been already tested cannot be used, thus requiring a new test. In this manner, an existing platform cannot be used not only for the temperature sensor portion but also for the integrated circuit portion, so that the fabrication cost of the semiconductor integrated circuit device increases. In addition, some types of material for the temperature sensor may contaminate the inside of the semiconductor integrated circuit device and an apparatus for fabricating the semiconductor integrated circuit device.